Microchip MPF050TL handleiding
Handleiding
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AC Switching Characteriscs
Data Sheet
© 2024 Microchip Technology Inc. and its subsidiaries
DS00003831E - 60
beyond the maximum specication shown in Table 5-36 when using single-ended congurations
(LVCMOS and LVTTL).
a. Tj increases by 8% for 0.5 ns < T
RISE
/T
FALL
≤ 2.0 ns.
b. Tj increases by 25% for 2.0 ns < T
RISE
/T
FALL
≤ 5.0 ns.
c. Tj increases by 35% for 0.5 ns < T
RISE
/T
FALL
≤ 5.0 ns.
5.4.5 Receiver Performance
The following table describes performance of the receiver.
Table 5-43. PolarFire Transceiver Receiver Characteriscs
Parameter Symbol Min Typ Max Unit Condition
Input voltage
range
V
IN
0 — V
DDA
+ 0.3 V —
Dierential
peak-to-peak
amplitude
V
IDPP
140 — 1250 mV —
Dierential
termination
V
ITERM
68 85 102 Ω 85Ω setting
80 100 120 Ω 100Ω setting
120 150 180 Ω 150Ω setting
Common mode
voltage
1
V
ICMDC
0.7 × V
DDA
— 0.9 × V
DDA
V DC coupled
Exit electrical
idle detection
time
T
EIDET
— 50 100 ns —
Run length of
consecutive
identical digits
(CID)
C
ID
— — 200 UI —
CDR frequency
tolerance
2
F
LRTOL
–11700 — +11700 ppm of line rate Enhanced
Receiver
Management is
disabled
14
CDR lock-to-
data time
13
T
LTD
512 * CDR
REFDIV
— 1024 *
CDR
REFDIV
CDR
REFCLK
cycles Enhanced
Receiver
Management is
disabled
14
(1900/T
CDRREF)
+
(512 + (1020 *
(W
XCVRFABRX
/
CDR
FBDIV
)) *
CDR
REFDIV
)
— (5200/T
CDRREF)
+
(1024 + (6380 *
(W
XCVRFABRX
/
CDR
FBDIV
)) *
CDR
REFDIV
)
CDR
REFCLK
cycles Enhanced
Receiver
Management is
enabled
14
CDR lock-to-ref
time
13
T
LTF
(1000/T
CDRREF
) +
(1024 *
CDR
REFDIV
)
— (13000/T
CDRREF
)
+ (1536 *
CDR
REFDIV
)
CDR
REFCLK
cycles —
High-gain lock
time
T
HGLT
10.8 — — ns For Burst Mode
Receiver (BMR)
High-gain state
time
12
T
HGSTATE
— — 3264 ns For Burst Mode
Receiver (BMR)
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Productinformatie
| Merk | Microchip |
| Model | MPF050TL |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 18409 MB |
