Microchip MPF050TL handleiding
Handleiding
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AC Switching Characteriscs
Data Sheet
© 2024 Microchip Technology Inc. and its subsidiaries
DS00003831E - 59
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Parameter Symbol Min Typ Max Unit Condition
Total jitter
5, 6, 13
Deterministic jitter
5, 6
T
J
T
DJ
— — 0.25
0.09
UI
UI
Data rate ≥5.0 Gbps to 8.5 Gbps
(Tx V
CO
rate 2.5 GHz to 4.25 GHz)
TxPLL in fractional mode
Total jitter
5, 6, 13
Deterministic jitter
5, 6
T
J
T
DJ
— — 0.17
0.03
UI
UI
Data rate ≥1.6 Gbps to 5.0 Gbps
(Tx V
CO
rate 1.6 GHz to 2.5 GHz)
TxPLL in integer mode
Total jitter
5, 6, 13
Deterministic jitter
5, 6
T
J
T
DJ
— — 0.2
0.03
UI
UI
Data rate ≥1.6 Gbps to 5.0 Gbps
(Tx V
CO
rate 1.6 GHz to 2.5 GHz)
TxPLL in fractional mode
Total jitter
5, 6, 13
Deterministic jitter
5, 6
T
J
T
DJ
— — 0.08
0.02
UI
UI
Data rate ≥ 800 Mbps to 1.6
Gbps (Tx V
CO
rate 1.6 GHz)
TxPLL in integer mode
Total jitter
5, 6, 13
Deterministic jitter
5, 6
T
J
T
DJ
— — 0.11
0.02
UI
UI
Data rate ≥ 800 Mbps to 1.6
Gbps (Tx V
CO
rate 1.6 GHz)
TxPLL in fractional mode
Total jitter
5, 6, 13
Deterministic jitter
5, 6
T
J
T
DJ
— — 0.05
0.01
UI
UI
Data rate = 250 Mbps to 800
Mbps (Tx V
CO
rate 1.48 GHz to
1.6 GHz)
TxPLL in integer mode
Total jitter
5, 6, 13
Deterministic jitter
5, 6
T
J
T
DJ
— — 0.06
0.01
UI
UI
Data rate = 250 Mbps to 800
Mbps (Tx V
CO
rate 1.48 GHz to
1.6 GHz)
TxPLL in fractional mode
1. Increased DC Common mode settings above 50% reduce allowed V
OD
output swing capabilities.
2. Adjustable through transmit emphasis.
3. With estimated package dierences.
4. Single PLL applies to all four lanes in the same quad location with the same TxPLL. Multiple PLL
applies to N lanes using multiple TxPLLs from dierent quad locations.
5. Improved jitter characteristics for a specic industry standard are possible in many cases due to
improved reference clock or higher V
CO
rate used.
6. Tx jitter is specied with all transmitters on the device enabled, a 10
–12
-bit error rate (BER) and Tx
data pattern of PRBS7.
7. From the PMA mode, the TX_ELEC_IDLE port to the XVCR TXP/N pins.
8. FTxRefClk = 75 MHz with typical settings.
9. For data rates greater than 10.3125 Gbps, V
DDA
must be set to 1.05V mode. See supply tolerance
in the section Recommended Operating Conditions.
10. Transmit alignment in this case will automatically align upon the Tx PLL obtaining lock. For
details on transmit alignment, see PolarFire Family Transceiver User Guide.
11. In order to obtain the required alignment for these congurations, an FPGA fabric Tx alignment
circuit must be implemented. For details on transmit alignment, see PolarFire Family Transceiver
User Guide.
12. Refclk skew is the amount of skew between the reference clocks of the two PLL.
13. Jitter decomposition can be found in the protocol characterization reports.
14. Tx total jitter (Tj) is quoted for reference clock rise and fall times as specied in Table 5-36. If
increased Tj is acceptable, the maximum reference clock input rise/fall times may be increased
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Productinformatie
| Merk | Microchip |
| Model | MPF050TL |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 18409 MB |
