Microchip MPF050TL handleiding
Handleiding
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AC Switching Characteriscs
Data Sheet
© 2024 Microchip Technology Inc. and its subsidiaries
DS00003831E - 54
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Parameter Symbol STD Min STD Typ STD Max –1 Min –1 Typ –1 Max Unit
Spread
spectrum
modulation
frequency
7
Mod_Freq TxREF
CLKPFD/
(128)
32 TxREF
CLKPFD/
(128*63)
TxREF
CLKPFD/
(128)
32 TxREF
CLKPFD/
(128*63)
KHz
1. See the maximum reference clock rate allowed per input buer standard.
2. The minimum value applies to this clock when used as an XCVR reference clock. It does not apply
when used as a non-XCVR input buer (DC input allowed).
3. Cascaded reference clock.
4. After reference clock input divider.
5. To calculate the F
TXREFPN
phase noise requirement at frequencies other than 156 MHz, use the
following formula: F
TXREFPN
at f(MHz) = F
TXREFPN
at 156 MHz + 20*log(f/156)
6. Programmable capability for depth of down-spread or center-spread modulation.
7. Programmable modulation rate based on the modulation divider setting (1 to 63).
8. If increased Tx total jitter is acceptable, the maximum reference clock input rise/fall times may
be increased beyond the maximum shown in this table when using single-ended congurations
(LVCMOS and LVTTL). Refer to Table 5-42 for total jitter specications as a function of reference
clock input rise/fall time
5.4.3 Transceiver Reference Clock I/O Standards
The following dierential I/O standards are supported as transceiver reference clocks.
• LVDS25/33
• HCLS25 (for PCIe)
• RSDS25/33
• MINILVDS25/33
• SUBLVDS25/33
• PPDS25/33
• SLVS25/33
• BUSLVDS25
• MLVDS25
• LVPECL33
• MIPI25
For DC input levels, see table Dierential DC Input and Output Levels.
The transceiver reference clock dierential receiver supports V
ICM
Common mode. If increased Tx
total jitter is acceptable, the maximum reference clock input rise/fall times may be increased beyond
the maximum specication shown in Table 5-36 when using single-ended congurations (LVCMOS
and LVTTL). Refer to Table 5-42 for jitter specication as a function of reference clock input rise/fall
time.
Note: The amount of jitter from the input receiver increases at Common modes of less 0.2V or
greater than XCVR
VREF
–0.4V. Therefore, for improved SerDes operation, it is recommended that the
V
CM
of the signal into the SerDes reference clock input be at a minimum of 0.2V and below XCVR
VREF
–0.4V.
The following single-ended I/O standards are supported as transceiver reference clocks.
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Productinformatie
| Merk | Microchip |
| Model | MPF050TL |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 18409 MB |
