Microchip MPF050TL handleiding
Handleiding
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AC Switching Characteriscs
Data Sheet
© 2024 Microchip Technology Inc. and its subsidiaries
DS00003831E - 52
Table 5-34. µPROM Performance
Parameter Symbol V
DD
= 1.0V
–STD
V
DD
= 1.0V
–1
V
DD
= 1.05V
–STD
V
DD
= 1.05V
–1
Unit
Read access time Tac 10 10 10 10 ns
5.4 Transceiver Switching Characteriscs
This section describes transceiver switching characteristics.
5.4.1 Transceiver Performance
The following table describes transceiver performance.
–STD speed grade is oered for Extended Commercial (E), Industrial (I), Military (M), and Automotive
(T2) temperature grades.
–1 speed grade is oered for Extended Commercial (E), Industrial (I), and Automotive (T2)
temperature grades only.
Table 5-35. PolarFire Transceiver and TxPLL Performance
Parameter Symbol STD Min STD Typ STD Max –1 Min –1 Typ –1 Max Unit
Tx data rate
1,2
F
TXRate
0.25 — 10.3125 0.25 — 12.7 Gbps
Tx OOB (serializer bypass) data rate F
TXRateOOB
DC — 1.5 DC — 1.5 Gbps
Rx data rate when AC coupled
2
F
RxRateAC
0.25 — 10.3125 0.25 — 12.7 Gbps
Rx data rate when DC coupled F
RxRateDC
0.25 — 3.2 0.25 — 3.2 Gbps
Rx OOB (deserializer bypass) data
rate
F
TXRateOOB
DC — 1.25 DC — 1.25 Gbps
TxPLL output frequency
3
F
TXPLL
1.6 — 5.1563 1.6 — 6.35 GHz
Rx CDR mode F
RXCDR
0.25 — 10.3125 0.25 — 10.3125 Gbps
Rx DFE and CDR auto-calibration
modes
2
F
RXAUTOCAL
3.0 — 10.3125 3.0 — 12.7 Gbps
Rx Eye Monitor mode
2
F
RXEyeMon
3.0 — 10.3125 3.0 — 12.7 Gbps
EQ far-end loopback data rate F
EQFELPB
0.25 — 1.25 0.25 — 1.25 Gbps
EQ near-end loopback data rate F
EQNELPB
0.25 — 10.3125 0.25 — 10.3125 Gbps
CDR far-end parallel loopback data
rate
6
F
CDRFELPB
0.00625
5
— 312.5 — — 312.5 MHz
PCS reset minimum pulse width MPW
PCS_RESET
16 — — 16 — — [Tx|Rx]_CLK
Cycles
4
PMA reset minimum pulse width MPW
PMA_RESET
16 — — 16 — — [Tx|Rx]_CLK
Cycles
4
1. The reference clock is required to be a minimum of 75 MHz for data rates of 10 Gbps and above.
2. For data rates greater than 10.3125 Gbps, V
DDA
must be set to 1.05V mode. See supply tolerance
in the section Recommended Operating Conditions.
3. The Tx PLL rate is between 0.5x to 5.5x the Tx data rate. The Tx data rate depends on per XCVR
lane Tx post-divider settings.
4. Minimum pulse width should reference TX_CLK when Tx only or both Tx and Rx are used.
Reference RX_CLK if only Rx is used.
5. In 40-bit wide parallel mode.
6. The CDR far-end parallel loopback is clocked by the recovered clock of the CDR. The bandwidth
of this loopback is equivalent to the clock multiplied by the data width.
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Productinformatie
| Merk | Microchip |
| Model | MPF050TL |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 18409 MB |
