Microchip MPF050TL handleiding

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AC Switching Characteriscs
Data Sheet
© 2024 Microchip Technology Inc. and its subsidiaries
DS00003831E - 48
Table 5-26. Period Jier for Transceiver Clocks
5, 6
Transceiver clocks are generated within the FPGA and routed to/from Transceiver TX and RX through global networks.
Jitter specications listed in this table are applicable to –STD and –1 speed grade for all temperature grades.
Parameter Transceiver Clock Period Jitter Unit
% FF used (of
total FFs in
device)
1,2
0% 15% 25% 50% 75% %
Average toggle
rate
3
30% 30% 30% 30% %
Eective FF
toggle %
4
0% 4.5% 7.5% 15.0% 22.5% %
Maximum TX
clock period
jitter (absolute)
60 89 114 228 287 ps
Maximum TX
clock period
jitter (peak to
peak)
±30 ±44.5 ±57 ±114 ±143.5 ps
Maximum RX
clock period
jitter (absolute)
200 229 254 368 427 ps
Maximum RX
clock period
jitter (peak to
peak)
±100 ±114.5 ±127 ±184 ±213.5 ps
1. % Flip-Flop (FF) used is dened as the percentage of total device FFs that are switching in the
largest clock domain within the FPGA (including synchronous and divided clocks).
2. The 50% and 75% FF used per clock domain are only shown to illustrate the impact of high
utilization on a global clock net jitter. Typical designs are expected to have less than 25% FF used
per clock domain (as dened in the preceding note).
3. Measured jitter is generated at varying % FF used levels with a switching rate of 30%.
4. Eective FF toggle % is the product of % FF used and average toggle rate. In Table 5-26, jitter is
specied for an average toggle rate of 30%. To determine jitter for a given combination, multiply
FF used and average toggle rate then use the linear interpolation equation as shown in Figure
5-6.
5. Refer to Table 5-27 for formulas to calculate period jitter as a function of the clocking topology.
6. For further details, see the PolarFire Family Transceiver Users Guide (section Global Net Clock
Jitter).

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Productinformatie

MerkMicrochip
ModelMPF050TL
CategorieNiet gecategoriseerd
TaalNederlands
Grootte18409 MB