Advantech PCL-833 handleiding
Handleiding
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17 PCL-833 User Manual
Chapter 3 Advanced Modes
DI0 latch
A rising edge on the board's DIO line will latch the counter value for the channel.
Dl1 latch
A rising edge on the Dl1 line will latch the counter value for the channel.
Timer latch
The card latches the counter value on a rising edge of pulses from the card's on-
board timer.
3.5 Counter Reset Values
Bit 3 (RF) of registers BASE+O, I and 2 control the initial (reset) value of for each
counter. You can select either 000000 or 800000(hex). When the counter is reset, it
will take this value.
When RF = 0, the counter will reset to 000000h
When RF = 1, the counter will reset to 800000h
3.5.1 Reset after latch
Bit 3 (LC) of registers BASE+3, 4 and 5 determine whether the corresponding
counter will reset to its initial value (see preceding section) when it is latched.
lf LC = I, the counter will reset to its initial value when it is latched
lf LC = 0, the counter will stay the same (keep its previous value)when it is latched.
3.6 Cascade Mode
24 bits is enough for most counter applications. If you need to store larger values,
you can cascade the output of one counter into the input of a second, giving 48 bits of
storage. When the first counter over-flows, the card increments the second counter.
The PCL-833 lets you cascade channel I into channel 2 to form a single 48-bit
counter. (Channel 3 will not cascade.)
The mode settings of channel I control this 48-bit counter, except that the setting of
channel 2 controls the initial (reset) value.
You set up the 48-bit counter as follows
1. Set bits CAS1 and CAS0 of write register BASE+8 to 0lh
2. Set CH2 to cascade mode. (Set Bits 0-2 of register BASE+1 to "111".
3. Set the initial (reset) value in CH2
4. Set remaining modes in CH1
To read the total value, you must read both counters. Channel 1 holds the high 24-
bits and channel 2 the low 24-bits.
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Productinformatie
Merk | Advantech |
Model | PCL-833 |
Categorie | Niet gecategoriseerd |
Taal | Nederlands |
Grootte | 1770 MB |