Advantech PCL-833 handleiding
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PCL-833 User Manual 16
3.3 Digital Noise Filter
Noise immunity is the most important requirement for reliable encoder interface oper-
ation. The PCL-833 conditions the input signals with a four stage digital filter. This fil-
ter reduces glitches (digital noise) or spikes by sampling the input at 2, 4 or 8 MHz.
The filter output waveforms change only when an input has the same value for three
consecutive sampling edges. The filter thus rejects noise or pulses shorter than two
sampling clock periods. You can optimize noise immunity by selecting the lowest
sampling frequency that compatible with the highest input rate you expect.
The PCL-833 accepts up to I MHz quadrature freq. at 8 MHz filter sampling speed. At
2 MHz sampling speed it can still accept up to 300KHz quadrature input freq.
A 3600 rpm motor with 2000 ppr encoder will have a max. quadrature freq. of 3600 x
200 0 / 60 = 120 KHz. In the above example the 2MHz sampling clock will have
the best noise immunity and will meet the required input freq.
The following table shows the maximum noise pulse width that the filter will reject for
each system clock frequency:
3.4 Latch Mode
When you read a counter, you are actually reading a value latched into a buffer. The
PCL-833 provides five different latching modes, only one of which is active at any
given time. Make sure that you know which latching mode is current whenever you
read the counter. Otherwise, you may read an old value or one that was latched at a
different time than you expect.
You select the latching mode for each channel individually. That is, you might select
S/W latching on channel I and DIO latching for channels 2 and 3. Bits 0-2 of register
BASE+3 control CHI, BASE+4control CH2 and BASE+5 control CH3.
The PCL-833's latching modes are as follows
S/W latch
Whenever you read a channel's data registers, the counter values will be latched in
buffer. The S/W latch will only take effect when you read the high byte of the counter
(C23-C16). Reading middle byte or low byte of a counter won't latch the counter val-
ues to the buffer. You should therefore read the high byte first, then the other two
bytes of the counter.
Index latch
A rising edge on the channel's index input line will latch the channel's counter value.
Clock freq. Maximum width
8MHz 375nsec
4MHz 750nsec
2MHz 1.5msec
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Productinformatie
| Merk | Advantech |
| Model | PCL-833 |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 1770 MB |
