Advantech PCIE-1812 handleiding
Handleiding
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vii PCIE-1812 User Manual
Figure 3.31Signed pulse (pulse/direction) mode. ....................... 40
Figure 3.32Position reset to 0 by counter Z signal ..................... 40
Figure 3.33Instant (software-timed) position measurement ....... 41
Figure 3.34Buffered (hardware-timed) position measurement ... 41
3.5.5 Position Comparison................................................................... 42
Figure 3.35Position Comparison ................................................ 42
Figure 3.36Instant position comparison...................................... 42
Figure 3.37Buffered position comparison ................................... 43
Figure 3.38Offset position comparison with offset value of “+2”. 43
3.5.6 One-Shot (Delayed Pulse Generation) ....................................... 44
Figure 3.39One-shot operation................................................... 44
3.5.7 Timer/Pulse................................................................................. 44
Figure 3.40Pulse output and timer interrupt ............................... 44
Figure 3.41Gated timer/pulse output .......................................... 44
Figure 3.42Static (software-timed) timer/pulse ........................... 45
Figure 3.43Buffered (hardware-timed) timer/pulse ..................... 45
3.5.8 Pulse Width Modulation Output .................................................. 46
Figure 3.44Pulse width modulation output.................................. 46
Figure 3.45Finite pulse generation ............................................. 46
Figure 3.46Infinite pulse generation ........................................... 46
Figure 3.47Gated pulse width modulation output ....................... 47
Figure 3.48Static (software-timed) timer/pulse ........................... 47
Figure 3.49Sample clock buffered pulse width modulation output .
48
Figure 3.50Implicit buffered pulse width modulation output........ 49
3.6 Timing Signals......................................................................................... 49
Figure 3.51Rising edge active digital trigger............................... 49
Figure 3.52Falling edge active digital trigger .............................. 49
Figure 3.53Rising edge active analog trigger ............................. 50
Figure 3.54Falling edge active analog trigger............................. 50
3.7 Synchronization....................................................................................... 51
3.7.1 MDSI (Multi-Device Synchronization Interface) Introduction ...... 51
Figure 3.55MDSI Layout............................................................. 51
3.7.2 MDSI Wiring................................................................................ 52
Figure 3.56Synchronize by External Cables............................... 52
Figure 3.57Signal Connection Synchronize by External Cables 52
Figure 3.58Synchronize by MDSI Cables................................... 53
Figure 3.59Signal Connection of MDSI Synchronize by MDSI Ca-
bles ........................................................................... 53
3.7.3 Types of MDSI ............................................................................ 54
Figure 3.60Synchronized-MDSI.................................................. 54
Figure 3.61Scanned-MDSI ......................................................... 55
3.7.4 MDSI Setting............................................................................... 55
Figure 3.62Setting for Primary Device........................................ 55
Figure 3.63Conversion Setting for Secondary Device................ 56
Figure 3.64Trigger Setting for Secondary Device....................... 56
Figure 3.65Data Logger for synchronization............................... 57
3.8 Calibration ............................................................................................... 57
Figure 3.66Calibration utility ....................................................... 57
3.9 Firmware/FPGA Code Update ................................................................ 58
Figure 3.67Firmware/FPGA code download utility ..................... 58
Appendix A Specifications ....................................59
A.1 Function Block Diagram .......................................................................... 60
Figure A.1 Function Block .......................................................... 60
A.2 Analog Input ............................................................................................ 61
Table A.1: -3 dB Bandwidth ....................................................... 61
Table A.2: Accuracy................................................................... 61
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Productinformatie
| Merk | Advantech |
| Model | PCIE-1812 |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 8115 MB |
