Advantech PCIE-1144-AE handleiding
Handleiding
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General Description CoaXPress Frame Grabbers
CXP-1-8 BitFlow, Inc. Version C.1
BitFlow’s frame grabbers. The acquisition circuit determines which pixels of which
lines of which frames are to be acquired. The correct pixels are then sent to a FIFO,
the output of which read by the DMA engine. The DMA engine then DMAs the data to
host memory.
CoaXPress cameras can output video on multiple links simultaneously. There is no
correlation between parts of the sensor and CXP links (like there is between sensor
taps and Camera Link taps). Any part of any line can be sent on any link in a multi-link
camera. The stream assembler must decode the packet headers and assemble raster
format lines.
1.2.7 Command and Control Packets
The second type of packet coming from the camera is a control packet. When the
board sees a control packet, it unwraps the packet and sends the contents into a con-
trol data FIFO. The host then reads and decodes this FIFO. Currently (as of CoaXPress
specification 1.1) control packets are synchronous. This means that the camera will
only send a control packet in response to a control packet sent from the host. For this
reason, software can be fully under control of the control packets sent from the cam-
era. It is not necessary to have an interrupt driven control packet circuit as there is for
serial communications in Camera Link. However, this may change with future revision
os the CoaXPress specification.
1.2.8 CXP Triggers
The third type of packet the Aon/Claxon/Cyton handle are the trigger packets. The
camera can send a trigger packet at any time. The Cyton-CXP maps the trigger packet
into the board’s trigger circuitry. It is one possible source for the internal trigger sig-
nal.
1.2.9 Uplink
CoaXPress provides a high speed uplink to control the camera. The uplink is also
packet based like the downlink. However, the uplink only supports two types of pack-
ets, control and Trigger. These packets are similar to the packets in the downlink. For
control packets, the BitFlow software builds up the packet in the board’s outgoing
control packet FIFO. Once the packet is fully built, a single bit sends the packet to the
camera. Trigger packets work in a similar manner, the trigger packet is a destination
for the board’s I/O system, and any number of sources can be routed to the CXP trig-
ger.
1.2.10 Cyton/Aon-CXP I/O system
The Cyton-CXP has a sophisticated I/O system, which is extremely flexible. The system
take in many inputs, routes them to a number of internal signals which can be further
manipulate, then routes the results to a wide rand of outputs. The I/O system is dis-
cuss in more detail in Section 7.1.
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Productinformatie
| Merk | Advantech |
| Model | PCIE-1144-AE |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 34568 MB |
