Advantech PCI-1742U handleiding
Handleiding
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21 Chapter 3
CNT0_CLK DGND Input Counter 0 Clock Input. The clock input of
counter 0 can be either external or inter-
nal , as set by software.
CNT0_OUT DGND Output Counter 0 Output.
CNT0_GATE DGND Input Counter 0 Gate Control.
PACER_OUT DGND Output Pacer Clock Output. This pin pulses
once for each pacer clock when turned
on. If A/D conversion is in the pacer trig-
ger mode, users can use this signal as a
synchronous signal for other applica-
tions.
TRG_GATE DGND Input A/D External Trigger Gate. When TRG
_GATE is connected to DGND, it will dis-
able the external trigger signal to input.
EXT_TRG DGND Input A/D External Trigger. This pin is external
trigger signal input for the A/D conver-
sion. A low-to-high edge triggers A/D
conversion to start.
+12V DGND Output +12 VDC Source.
+5V DGND Output +5 VDC Source.
Table 3.1: I/O Connector Signal Description
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Productinformatie
| Merk | Advantech |
| Model | PCI-1742U |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 5110 MB |
