Advantech MIC-3332 handleiding
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43 MIC-3332 User Manual
Appendix C FPGA Specification
Power Sequencing and Platform Control
– Generates the right power up and down sequencing
– Monitors power supplies and disable power supplies if needed
– generate reset signals
BIOS CS SWTICH
– Switch to backup BIOS when major BIOS crash
C.3 FPGA I/O Registers
The Advantech MIC-3332 FPGA communicates with main I/O spaces. The LPC unit
is used to interconnect the Intel CM236 LPC signals. This chapter will list down all
registers with a short description off the register interface. A detailed explanation can
be found in the regarding function block description.
Register Address: IO address 440h-441h
Register Name: FPGA Vandor ID Register
Default Value: 13FE
Attribute: Read Only
Table C.1: Register Map
Reg-Nr.: Mnemonic
R/W
LPC
default
Ox
Function
LPC
Address Ox
0 0 FPGA Vandor ID RO 13 FPGA Vandor ID[15:8] 440
1 1 FPGA Vandor ID RO FE FPGA Vandor ID[7:0] 441
2 2 OS ShutDown Register R/W 00 OS ShutDown Flag 442
3 3 Watchdog Count Value R/W 00
Watchdog Count
Value
443
4 4 Watchdog Function R/W 80
Read for disabling
bios switch
444
5 5 FPGA Device ID RO 33 FPGA Device ID[15:8] 445
6 6 FPGA Device ID RO 32 FPGA Device[7:0] 446
7 7 Revision ID RO 00 Revision ID[15:8] 447
8 8 Revision ID RO 01 Revision ID[7:0] 448
9 9 Power Status RO 00 Power Status 449
10 A GA Status RO 00 GA Status 44a
11 B GPIO Input Status RO 00 GPIO Input Status 44b
12 C GPIO Output Value R/W 00 GPIO Output Value 44c
13 D GPIO Output Enable R/W 00 GPIO Output Value 44d
14 E Port 80 Status RO 00 Port 80 Status 44e
15 F Dual BIOS Switch Register R/W 00 Dual BIOS Switch 44f
Bit Description Access
15-0
Vandor ID
This field identifies the particular device.
This is a 16-bit value assigned to Advantech Co., Ltd.
RO
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Productinformatie
| Merk | Advantech |
| Model | MIC-3332 |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 8943 MB |
