Advantech ITA-520 handleiding
Handleiding
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I28 TA-520 User Manual
Chapter 4 AMI BIOS
4.4.5 I ntel(R) Time Coordinated Computing
Figure 4.14 Intel(R) Time Coordinated Computing
#AC Split Lock
Enable or Disable Alignment Check Exception (#AC). When enabled, this will
assert an #AC when any atomic operation has an operand that crosses two
cache lines.
IFU Enable
Enable or Disable Instruction Fetch Unit (IFU). When enabled, Instructions will
be prefetch to the cache.
Intel(R) TCC Authentication Menu
Intel(R) TCC Authentication Menu options.
Intel(R) TCC Mode
Enable or Disable Intel(R) TCC Mode. When enabled, this will modify system
settings to improve real-time performance. The full list of settings and their cur-
rent state are displayed below when Intel(R) TCC mode is enabled.
IO Fabric Low Latency
Enable or Disable IO Fabric Low Latency. This will turn off some power manage-
ment in the PCH IO fabrics. This option provides the most aggressive IO Fabric
performance setting. S3 state is NOT supported.
OPIO Recentering
Enable or Disable Opio Recentering to improve Pcie latency.
C states
Enable/Disable CPU Power Management. Allows CPU to go to C states when
it's not 100% utilized.
Intel(R) Speed Shift Technology
Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose
the CPPC v2 interface to allow for hardware controlled P-states.
Bekijk gratis de handleiding van Advantech ITA-520, stel vragen en lees de antwoorden op veelvoorkomende problemen, of gebruik onze assistent om sneller informatie in de handleiding te vinden of uitleg te krijgen over specifieke functies.
Productinformatie
| Merk | Advantech |
| Model | ITA-520 |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 8599 MB |
