Advantech AIW-356 handleiding
Handleiding
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Figure 3-9 Reset timing 2
nd
Index
Min.
Recommended
Max.
Remarks
t
off1
16ms
20ms
-
Pull-down delay time of RESET# signal relative to PERST#.
For details, refer to section 3.3.2
t
off2
0
-
-
Pull-down delay time of FCPO# signal relative to RESET#.
For details, refer to section 3.3.2
t
off
500ms
500ms
-
Power-off time must be not less than 500ms to ensure the
module is completely discharged
t
on1
0
-
-
Delay time of RESET# signal relative to FCPO#.
For details, refer to section 3.3.1.2
t
on2
50ms
100ms
-
Delay time of PERST# signal relative to FCPO# signal.
PERST# must always be the last signal to pull up during
power-on.
For details, refer to section 3.3.1.2
Table 3-11 Reset timing
Note:
2. RESET# is a sensitive signal, it’s recommended to add a filter capacitor near the module. In
case of PCB layout, the RESET# signal lines should be kept away from the RF interference
and protected by GND. Also, the RESET# signal lines shall be kept away from the PCB
edge and the surface planes to avoid module reset caused by ESD problems.
3. If the PCIe and USB interfaces are connected to the host, and USB is used as the data
transmission interface, the PERST# timing can be ignored.
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Productinformatie
| Merk | Advantech |
| Model | AIW-356 |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 8839 MB |
