Microchip MPF500TS handleiding
Handleiding
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Board Components and Operations
Microchip UG0786 Revision 5 14
4.4 Microchip PHY (VSC8541)
The VSC8541 device, offered in a small (8 mm × 8 mm), single-row, quad-flat no-leads (QFN) package is
designed for space-constrained 10/100/1000BASE-T applications. It features integrated line-side
termination to conserve board space, lower electromagnetic induction (EMI), and improve system
performance. Additionally, the integrated RGMII version 2.0 standard timing-compliant compensation
eliminates the need for on-board delay lines.
The device supports the industry’s widest range of LVCMOS levels for a parallel MAC interface, including
1.5 V, 1.8 V, 2.5 V, and 3.3 V. It also supports 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V for the MDIO/MDC
interface. The device includes Microchip EcoEthernet™ 2.0 technology with energy-efficient Ethernet
and other power saving features that reduce power based on link state and cable reach. These features
enable the device to optimize power consumption at all link operating speeds.
Figure 9 • PHY Interface
4.5 Power Monitoring
The PolarFire Splash Board uses a Microchip A2F200M3F-1FGG256I device to monitor the voltage rails.
The A2F200M3F-1FGG256I device is programmed through the FTDI interface, and it supports the UART
interface. The device needs an external 20-MHz crystal frequency.
Key features of Microchip A2F200M3F-1FGG256I are:
• Microcontroller subsystem (MSS)
• Analog compute engine (ACE)
• Programmable analog front-end (AFE)
For more information about how to monitor power on the board, see Appendix: Power Monitoring,
page 27.
PolarFire FPGA
Microchip PHY
VSC8541
MDC/MDIO
ETH_TXD[0:3]
ETH_RXD[0:3]
GPIO – Bank4
Port0
RJ45
4 Pairs
25MHz
Crystal
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Productinformatie
| Merk | Microchip |
| Model | MPF500TS |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 5215 MB |
