Microchip MPF500TS handleiding
Handleiding
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Board Components and Operations
Microchip UG0786 Revision 5 12
Figure 6 • XCVR0 Interface
4.3.2 XCVR1 Interface
The XCVR1 interface has one lane that is connected to FMC LPC connector. The signals are routed in
the PCB as follows:
• Lanes 0 is directly routed to the FMC LPC connector.
• TX pad > trace > via (to top layer) > trace > FMC LPC connector pad
• RX pad > trace > via (to top layer) > trace > PolarFire device pad
The XCVR1 reference clock is routed directly from the LPC connector to the PolarFire device.
The following figure shows the XCVR1 interface of the PolarFire Splash Board.
PolarFire FPGA
Lane0/ RXD
Lane1/ RXD
Lane2/ RXD
Lane3/ RXD
PCIe Edge
connector
Lane0/ TXD
Lane1/ TXD
Lane2/ TXD
Lane3/ TXD
REFCLK0
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Productinformatie
| Merk | Microchip |
| Model | MPF500TS |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 5215 MB |
