Microchip MPF500TS handleiding
Handleiding
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Board Components and Operations
Microchip UG0786 Revision 5 10
4 Board Components and Operations
This section describes the key components of the PolarFire Splash Board and provides information
about important board operations. For device datasheets, visit the PolarFire Kits webpage.
4.1 DDR4 Memory Interface
Two 4-Gb DDR4 SDRAM chips are provided to serve as flexible volatile memory for user applications.
The DDR4 interface is implemented in HSIO bank0 and bank1.
The DDR4 SDRAM specifications for the PolarFire device are:
• Two IS43QR16256A chips connected in fly-by topology
• Density: 1 GB
• Data rate: DDR4 32-bit at 200 MHz clock rate
The DDR4 memory operates at 1600 MHz with gearing 1:8 for the 200-MHz PolarFire fabric.
The PolarFire Splash Board design uses the DDR4 and POD12 standards for the DDR4 interface. The
default board assembly available for the DDR4 standard has RC terminations.
Figure 4 • DDR4 Memory Interface
For more information, see the Board Level Schematics document (provided separately).
4.2 SPI Serial Flash
The SPI flash specifications for the PolarFire device are:
• Density: 1 Gb
• Voltage: 2.7 V to 3.6 V (MT25QL01GBBB8ESF-0SIT)
• Frequency: 90 MHz
• Quantity: 1
• SPI mode support: Modes 0 and 3
• Dedicated bank: Bank3
DQS/DQS#[3:0]
Data DQ[31:0]
DDR4 SDRAM
256M×16 (1 GB)
2 memory chips
Address A[13:0]
Control lines
DDR4 Chips
PolarFire FPGA
HSIO-BANK0, 1
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Productinformatie
| Merk | Microchip |
| Model | MPF500TS |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 5215 MB |
