Microchip MPF200TL handleiding
Handleiding
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DC Characteriscs
Data Sheet
© 2024 Microchip Technology Inc. and its subsidiaries
DS00003831E - 8
...........continued
Parameter Symbol Min Typ Max Unit Condition
Transceiver Tx and Rx lanes supply (1.0V
mode)
6, 7
V
DDA
0.97 1.00 1.03 V When all lane rates are 10.3125
Gbps or less.
1
Transceiver Tx and Rx lanes supply
(1.05V mode)
6
V
DDA
1.02 1.05 1.08 V Must when any lane rate is
greater than 10.3125 Gbps.
Lane rates 10.3125 Gbps or less
may also be powered in 1.05V
mode.
1
Programming and HSIO receiver supply
6
V
DD18
1.71 1.80 1.89 V —
FPGA core and FPGA PLL high-voltage
supply
6
V
DD25
2.425 2.50 2.575 V —
Transceiver PLL high-voltage supply
6
V
DDA25
2.425 2.50 2.575 V —
Transceiver reference clock supply
6, 7
V
DD_XCVR_CLK
3.135 3.3 3.465 V 3.3V nominal
2.375 2.5 2.625 V 2.5V nominal
Global V
REF
for transceiver reference
clocks
3
XCVR
VREF
Ground — V
DD_XCVR_ CLK
V —
HSIO DC I/O supply
6
V
DDIx
1.14 Various 1.89 V Allowed nominal options: 1.2V,
1.35V, 1.5V, and 1.8V
4, 5
GPIO DC I/O supply
6
V
DDIx
1.14 Various 3.465 V Allowed nominal options: 1.2V,
1.5V, 1.8V, 2.5V, and 3.3V
2, 4, 5
Dedicated I/O DC supply for JTAG and
SPI (GPIO Bank 3)
6
V
DDI3
1.71 Various 3.465 V Allowed nominal options: 1.8V,
2.5V, and 3.3V
GPIO auxiliary supply
6
V
DDAUXx
3.135 3.3 3.465 V For I/O bank x with V
DDIx
= 3.3V
nominal
2, 4, 5
2.375 2.5 2.625 V For I/O bank x with V
DDIx
= 2.5V
nominal or lower
2, 4, 5
Extended commercial temperature
range
T
J
0 — 100 °C —
Industrial temperature range T
J
–40 — 100 °C —
Automotive T2 temperature range T
J
–40 — 125 °C —
Military temperature range T
J
–55 — 125 °C —
Extended commercial programming
temperature range
T
PRG
0 — 100 °C —
Industrial programming temperature
range
T
PRG
–40 — 100 °C —
1. V
DD
and V
DDA
can independently operate at 1.0V or 1.05V nominal. These supplies are not
dynamically adjustable.
2. For GPIO buers where I/O bank is designated as bank number, if V
DDIx
is 2.5V nominal or 3.3V
nominal, V
DDAUXx
must be connected to the V
DDIx
supply for that bank. If V
DDIx
for a given GPIO
bank is <2.5V nominal, V
DDAUXx
per I/O bank must be powered at 2.5V nominal.
3. XCVR
VREF
globally sets the reference voltage of the transceiver's single-ended reference clock
input buers. It is typically near V
DD
_
XCVR
_CLK
/2V but is allowed in the specied range.
4. The power supplies for a given I/O bank x are shown as V
DDIx
and V
DDAUXx
.
5. At power-up and power-down, the V
DDIx
and V
DDAUXx
supply sequencing can cause signal
glitches. Refer to PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide and UG0726:
PolarFire FPGA Board Design User Guide for detailed explanation and recommended steps.
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Productinformatie
| Merk | Microchip |
| Model | MPF200TL |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 18409 MB |
