Microchip MPF200TL handleiding
Handleiding
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AC Switching Characteriscs
Data Sheet
© 2024 Microchip Technology Inc. and its subsidiaries
DS00003831E - 42
9. Programmable modulation rate based on the modulation divider setting (1 to 63).
10. Period jitter is measured at the output of the device using HSUL12 output buers and includes
the jitter eects of the reference clock source, PLL, clock routing networks, and output buer.
PLL is congured with internal feedback enabled and in integer mode. FPGA fabric is active
during testing (75% utilization).
11. Jitter characteristics for protocol-specic industry standards are met due to improved input
clock path and/or optimized VCO rates used. Contact technical support for protocol specic
characterization reports.
Note: In order to meet all datasheet specications, the PLL must be programmed such that the PLL
Loop Bandwidth < (0.0017 * VCO Frequency) – 0.4863 MHz. The Libero PLL conguration tool will
enforce this rule when creating PLL congurations.
5.2.3 DLL
The following table provides information about DLL.
Table 5-19. DLL Electrical Characteriscs
Parameter
1
Symbol Min Typ Max Unit
Input reference clock frequency F
INF
133 — 800 MHz
Input feedback clock frequency F
INFDBF
133 — 800 MHz
Primary output clock frequency F
OUTPF
133 — 800 MHz
Secondary output clock frequency
2
F
OUTSF
33.3 — 800 MHz
Input clock cycle-to-cycle jitter F
INJ
— — 200 ps
Output clock cycle-to-cycle jitter (with clean input clock) T
OUTJITTERCC
— — Max (250 ps, 15% of
clock period)
ps
Output clock period jitter (with clean input clock) T
OUTJITTERP
— — Max (300 ps, 20% of
clock period)
ps
Output clock-to-clock skew between two outputs with
the same phase settings
T
SKEW
— — ±150 ps
DLL lock time T
LOCK
16 — 16K Reference clock
cycles
Minimum reset pulse width T
MRPW
3 — — ns
Minimum input pulse width
3
T
MIPW
20 — — ns
Minimum input clock pulse width high T
MPWH
400 — — ps
Minimum input clock pulse width low T
MPWL
400 — — ps
Delay step size T
DEL
12.7 30 35 ps
Maximum delay block delay
4
T
DELMAX
1.8 4.8 ns
Output clock duty cycle (with 50% duty cycle input)
5
T
DUTY
40 — 60 %
Output clock duty cycle (with 50% duty cycle input)
6
T
DUTY50
45 — 55 %
1. For all DLL modes.
2. Secondary output clock divided by four option.
3. On load, direction, move, hold, and update input signals.
4. 128 delay taps in one delay block.
5. Without duty cycle correction enabled.
6. With duty cycle correction enabled.
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Productinformatie
| Merk | Microchip |
| Model | MPF200TL |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 18409 MB |
