Microchip MPF100TS handleiding

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Handleiding

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Getting Started
Microchip UG0786 Revision 5 3
2.2 Block Diagram
The following block diagram shows all the components of the PolarFire Splash Board.
Figure 1 • PolarFire Splash Board Block Diagram
2.3 Web Resources
For more information about the PolarFire Splash Board, see PolarFire Splash Kit webpage.
2.4 Board Overview
The PolarFire Splash Board features a PolarFire MPF300T-1FCG484E FPGA with the following
capabilities:
20-Kb dual-port or two-port LSRAM block with a built-in single error correct double error detect
(SECDED) capability
64 × 12 two-port µSRAM block implemented as an array of latches
18 × 18 multiply-accumulate (MACC) block with a pre-adder, a 48-bit accumulator, and an optional
16 deep × 18 coefficient RO
Built-in µPROM, modifiable at program time and readable at run time, for user data storage
Digest integrity check for FPGA, µPROM, and sNVM
Low-power features:
Low device static power
Low inrush current
VSC8541XMV
PHY
FT4232
USB mini B
connector
ETH_RXD[0:3]
JTAG
Bank3
DDR4
IS43QR16256A
8 Gb (256M*32)
HSIO
Bank0, 1
Lane 1
Debug LEDs-8
GPIO
Bank4
XCVR1_Lane1
GPIO
Bank4
A2F200M3F-
1FGG256I
Jumper
J5, 6, 7, 8, 9
Port A
JTAG
DE
MUX
0
1
MUX
U36
U15
JTAG
Header
0
1
J15
MUX
U16
SPI
External
Flash (1 Gb)
U33
1
0
SC-SPI
Bank3
S
S
SPI SIGNALS
JTAG
SIGNALS
UART
Debug Switches-4
GPIO
Bank4
J5
GPIO
Bank4
UART
SIGNALS
S
On-Board
Oscillator 50 MHz
RJ45
10/100/1000
Mbps
Port C
Port D
PCIe Edge
Connector
LPC[0:33]
XCVR0
Lane 4 REFCLK0
CON1
On-Board
Oscillator
125 MHz
XCVR_0A_
REFCLK
XCVR_0C_
REFCLK
System_Controller
The JTAG programming data goes to
the System_Controller and then from
SC_SPI bank3 it goes to the external
SPI flash device.
J11 Jumper
GND
GND
J11 Jumper
J10 Jumper
GND
GPIO
Bank4
MPF300T-1FCG484E
FMC LPC Connector
XCVR1 Lane 0
J17
XCVR Lane
GPIO Bank2
25 MHz
Crystal
ETH_TXD[0:3]
XCVR1_Lane2
XCVR1_Lane3
Lane 3 to 2

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Productinformatie

MerkMicrochip
ModelMPF100TS
CategorieNiet gecategoriseerd
TaalNederlands
Grootte5215 MB