Microchip MPF100TS handleiding
Handleiding
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Board Components and Operations
Microchip UG0786 Revision 5 16
The following figure shows the FTDI interface of the PolarFire Splash Board.
Figure 11 • FTDI Interface
4.7 System Reset
DEVRST_N is an input-only reset pad that allows a full reset of the chip to be asserted at any time. The
following figure shows a sample reset circuit that uses a Microchip MCP121T-240E/TT device.
Figure 12 • Reset Circuit
4.8 50-MHz Oscillator
A 50-MHz clock oscillator with an accuracy of +/-50 ppm is available on the board. This clock oscillator is
connected to the FPGA fabric to provide a system reference clock.
An on-chip PolarFire phase-locked loop (PLL) can be configured to generate a wide range of high-
precision clock frequencies.
The pin number of the 50-MHz oscillator is H7, and the pin name is
GPIO239PB5/CLKIN_W_2/CCC_SW_CLKIN_W_2/CCC_SW_PLL0_OUT0.
The following figure shows the 50-MHz clock oscillator interface.
Figure 13 • 50-MHz Clock Oscillator
For more information, see the Board-Level Schematics document (provided separately).
FT4232
USB mini B
connector
A2F200M3F-1FGG256I
J5, 6, 7, 8, 9
Port A
JTAG
DE
MUX
0
1
MUX
U36
U15
JTAG
Header
0
1
J15
MUX
U16
SPI
External Flash
(1 Gb)
1
0
S
S
SPI SIGNALS
JTAG
SIGNALS
UART
J5
UART SIGNALS
S
Port C
Port D
J11
GND
GND
J11
J10
GND
PolarFire FPGA
Bank4
Bank3
Bank3
MCP121T-
240E/TT
Bank3
DEVRST_n
VDD25
50 MHz
Oscillator
PolarFire
FPGA
3.3 V
H7
Bank4
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Productinformatie
| Merk | Microchip |
| Model | MPF100TS |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 5215 MB |
