Microchip LN-CSAC-SA65 handleiding
Handleiding
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LN-CSAC Model SA65-LN User’s Guide
DS50003805A-page 16 2024 Microchip Technology Inc. and its subsidiaries
When the LN-CSAC is initially powered on, it performs an acquisition sequence, which
includes stabilizing the temperature of the physics package, optimizing physics pack-
age operating parameters, and acquiring frequency lock to the atomic resonance. The
acquisition process may be monitored through the status field of the telemetry (see
Section 3.3.1 “Telemetry (6 and ^)”). On power-up, the status begins at 8 (oven
warm-up). The status value decrements numerically through the acquisition until nor-
mal operation (status = 0) is achieved. On rare occasions, the status countdown will
reset during the acquisition. This is normal behavior if it does not disrupt the
time-to-lock specification.
Note 1: R. Lutwak, et. al., The Chip-Scale Atomic Clock - Low-Power Physics
Package, Proceedings of the 36th Annual Precise Time and Time Interval
(PTTI) Systems and Applications Meeting, December 7–9, 2004, Wash-
ington, DC.
2: R. Lutwak, et. al., The MAC - A Miniature Atomic Clock, Proceedings of the
2005 Joint IEEE International Frequency Control Symposium and Precise
Time & Time Interval Systems & Applications Meeting, August 29–31,
2005, Vancouver, BC.
2.2 START-UP SEQUENCE
When power is connected to pin 5 the LN-CSAC unit begins its warm-up cycle. 10 MHz
and 1 PPS output signals appear immediately upon power-up, but the output signals
are not stable until the atomic control loop is locked (indicated CMOS low on the BITE
pin and also by the "status" telemetry field).
Within 3 minutes at 25°C, the LN-CSAC achieves Lock and BITE = 0
(Section 2.3 “Built-in Test Equipment (BITE)”). Power consumption during warm-up
is greater than during normal operation; as specified on the LN-CSAC data sheet.
It is recommended to always allow the LN-CSAC to remain powered on for >120 sec-
onds after it acquires LOCK, after which the LN-CSAC will store the recently acquired
set points to memory. Allowing the LN-CSAC to periodically store its set points mini-
mizes the possibility of the LN-CSAC subsequently powering on with obsolete set
points. Otherwise, upon the next power up, the unit may need to reacquire its set points
and time-to-lock may be out of specification.
2.3 BUILT-IN TEST EQUIPMENT (BITE)
While the preferred method for monitoring LN-CSAC state of health is with the "status"
parameter, it can also be monitored electronically on pin 6 (BITE) of the LN-CSAC. Fre-
quency lock is indicated both by status = 0 in the status field of telemetry and by the
electrical state of the BITE output pin, which is high (logic 1) upon initial power-on and
whenever status ≠ 0. The BITE pin is a high impedance CMOS logic output.
CAUTION
To avoid severe damage to the unit, do not apply power to the incorrect terminals. The
LN-CSAC does not have reverse voltage protection.
Note: When not locked, BITE = 1 and status ≠ 0 in the status field of the telemetry
output string.
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Productinformatie
| Merk | Microchip |
| Model | LN-CSAC-SA65 |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 6392 MB |
