Advantech PCM-3718H handleiding
Handleiding
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PCM-3718 Series User Manual 38
INT Data valid.
0 No A/D conversion has been completed since the last
time the INT bit was cleared. Values in the A/D data reg-
isters are not valid data.
1 The A/D conversion is completed, and converted data is
ready. If the INTE bit of the control register (BASE+9)
is set, an interrupt signal will be sent to the PC bus
through interrupt level IRQn, where n is specified by bits
I2, I1 and I0 of the control register. Though the A/D sta-
tus register is read-only, writing to it with any value
clears the INT bit.
CN3 to CN0 When EOC = 0, these status bits contain the channel
number of the next channel to be converted.
Remarks
If you trigger the A/D conversion by the onboard pacer, your software
should check the INT bit, not the EOC bit, before it reads the conversion
data.
EOC can equal 0 in two different situations: the conversion is completed
or no conversion has been started. Your software should therefore wait for
the signal INT = 1 before it reads the conversion data. It should then clear
the INT bit by writing any value to the A/D status register BASE+8.
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Productinformatie
| Merk | Advantech |
| Model | PCM-3718H |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 5483 MB |
