Advantech PCI-1721 handleiding
Handleiding
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Chapter 2
– 14 –PCI-1721 User’s Manual
Advantech Co., Ltd.
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I/O Connector Signal Description
Table 2-2 I/O Connector Signal Description
Fig. 2-3 FIFO block diagram of PCI-1721
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Vout<0..3> AGND Output Voltage Output, Channels 0 through 3.
Iout<0..3> AGND Output Current Output, Channels 0 through 3.
REF_V<0..3> AGND Input External Reference, Channel 0 through 3.
AGND - -
Analog Ground. The two ground references (AGND and DGND) are
connected together on the PCI-1721 card.
REF_10V AGND Output +10 VDC Reference.
REF_5V AGND Output +5 VDC Reference.
DI0<0..15> DGND -
Digital Input / Output signals. These pins are digital input / Output channel
0 to 15.
DGND - -
Digital Ground. The two ground references (AGND and DGND) are
connected together on the PCI-1721 card.
CNT0_CLK DGND Input
Counter 0 Clock Input. The clock input of counter 0 can be either external
(up to 10 MHz) or internal (1 MHz), as set by software.
CNT0_OUT DGND Output Counter 0 Output.
CNT0_GATE DGND Input Counter 0 Gate Control.
FIFO_OUT DGND Output
FIFO Output. This pin pulses once for each FIFO clock when turned on. If
D/A conversion is in the FIFO trigger mode, users can use this signal as a
synchronous signal for other applications. A low-to-high edge triggers D/A
conversion to start.
EXT_GATE DGND Input
D/A External Trigger Gate. When EXT_GATE is connected to +5 V, it
will enable the external trigger signal to input. When EXT_GATE is connected
to DGND, it will disable the external trigger signal to input.
EXT_CLK DGND Input
D/A External Trigger Clock. This pin is external trigger clock input for the
D/A conversion. A low-to-high edge triggers D/A conversion to start.
+12V DGND Output
+12 VDC Source
(from PCI bus directly with FUSE protection).
+5V DGND Output +5 VDC Source (from PCI bus directly with FUSE protection).
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Productinformatie
| Merk | Advantech |
| Model | PCI-1721 |
| Categorie | Niet gecategoriseerd |
| Taal | Nederlands |
| Grootte | 5476 MB |
