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15 IDK-1112R-50XGA1 User Manual
Chapter 2 LCD Display
2.7 Interface Timing
2.7.1 Input Signal Timing Specifications
The input signal timing specifications are shown as the following table and timing dia-
gram.
INPUT SIGNAL TIMING DIAGRAM
Table 2.7: Display Timing Specifications
Signal Item Symbol Min. Typ. Max. Unit Note
DCLK Frequency Fc 57.5 64.9 74.4 MHz
Vertical Active Dis-
play Term
Total Tv 774 806 848 Th Th=Tvd+Tvb
Display Tvd - 768 - Th -
Blank Tvb 6 38 80 Th -
Horizontal
Active Display
Term
Total Th 1240 1344 1464 Tc Th=Thd+Thb
Display Thd - 1024 - Tc
Blank Thb 216 320 440 Tc -
Note (1) Since this assembly is operated in DE only mode, Hsync and Vsync
input signals should be set to low logic level. Otherwise, this assembly
would operate abnormally.
Note (2) Frame rate is 60Hz
Note (3) The Tv(Tvd+Tvb) must be integer, otherwise, this module would operate
abnormally.
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Productinformatie
| Merk | Advantech |
| Model | IDK-1112 |
| Categorie | Monitor |
| Taal | Nederlands |
| Grootte | 4196 MB |
